@article{231c1d44626d49f585947d616d4d1a3d,
title = "The SARC architecture",
abstract = "The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.",
author = "Alex Ramirez and Felipe Cabarcas and Ben Juurlink and {Alvarez Mesa}, Mauricio and Friman Sanchez and Arnaldo Azevedo and Cor Meenderinck and Catalin Ciobanu and Sebastian Isaza and Gerogi Gaydadjiev",
note = "Funding Information: We thank the rest of the team that developed the TaskSim simulator: Alejandro Rico, Carlos Villavieja, Augusto Vega, Toni Ques-ada, Milan Pavlovic, and Yoav Etsion. We also thank Pieter Bellens for his help obtaining the application traces. This research was supported by the SARC project (FP6-FET-27648), and the Consolider contract TIN2007-60625 from the Ministry of Science and Innovation of Spain. Felipe Cabarcas was also supported by the Program AlBan, the European Union Program of High Level Scholarships for Latin America (scholarship No. E05D058240CO). Finally, we recognize Man-olis Katevenis for his participation in the definition of the SARC architecture, and Stamatis Vassiliadis and Mateo Valero, who made the SARC project happen in the first place.",
year = "2010",
month = sep,
doi = "10.1109/MM.2010.79",
language = "English (US)",
volume = "30",
pages = "16--29",
journal = "IEEE Micro",
issn = "0272-1732",
publisher = "IEEE Computer Society",
number = "5",
}